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ADP3419
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
IN
SD
DRVLSD
CROWBAR
VCC
DRVL
GND
SW
DRVH
BST
Description
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling
this pin low turns on the low-side driver; pulling it high turns on the high-side driver.
Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled
and controlled by IN and by the adaptive overlap protection control circuitry.
Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition.
Input Supply. This pin should be bypassed to GND with a 4.7 m F or larger ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the
switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched.
ELECTRICAL CHARACTERISTICS V CC = SD = 5.0 V, BST = 4.0 V to 26 V. T A = 0 ° C to 100 ° C, unless otherwise noted All limits at
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)
Input Voltage High
Input Voltage Low
V IH
V IL
2.0
0.8
V
V
Input Current
DRVLSD Propagation Delay Time
I IN
t pdl D RVLSD ,
t pdh DRVLSD
Inputs = 0 V or 5.0 V
C LOAD = 3 nF, Figure 3
? 1.0
20
+1.0
m A
ns
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
BST ? SW = 4.6 V
BST ? SW = 4.6 V
1.7
0.8
3.3
2.3
W
W
Transition Times
t rDRVH
t fDRVH
BST ? SW = 4.6 V, C LOAD = 3 nF, Figure 4
BST ? SW = 4.6 V, C LOAD = 3 nF, Figure 4
14
11
35
25
ns
Propagation Delay Times (Note 1)
t pdhDRVH
t pdlDRVH
BST ? SW = 4.6 V, C LOAD = 3 nF, Figure 4
BST ? SW = 4.6 V, C LOAD = 3 nF, Figure 4
15
32
28
70
60
ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
1.7
0.8
3.3
2.3
W
W
Transition Times
Propagation Delay Times (Note 2)
t rDRVL
t fDRVL
t pdhDRVL
t pdlDRVL
C LOAD = 3 nF, Figure 4
C LOAD = 3 nF, Figure 4
C LOAD = 3 nF, Figure 4
C LOAD = 3 nF, Figure 4
13
11
25
16
30
25
48
30
ns
ns
SW Transition Timeout (Note 1 and 2)
t SWTO
BST ? SW = 4.6 V
150
350
600
ns
Zero-Crossing Threshold
V ZC
1.0
V
SUPPLY
Supply Voltage Range
V CC
4.6
6.0
V
Supply Current
Normal Mode
Shutdown Mode
I SYS(NM)
I SYS(SD)
I CC + I BST , IN = 0 V or 5.0 V
I CC + I BST , SD = 0 V
0.8
325
1.5
600
mA
m A
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
(Note 3)
V CC rising
V CC falling
3.8
50
4.25
120
4.5
V
mV
1. For propagation delays, t pdh refers to the specified signal going high, and t pdl refers to the signal going low with transitions measured at 50%.
2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of t SWTO .
3. Guaranteed by characterization, not production tested.
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